Technical Field
The present disclosure relates to communication systems and methods.
The disclosure has been developed with particular attention paid to its possible use for providing communication within integrated circuits that comprise circuits that use various clock signals (multi-clock circuits).
Description of the Related Art
Systems within an integrated circuit (Systems-on-Chip or SoCs), such as for example circuits designed for mobile or multimedia applications, frequently use various circuits of the IP (Intellectual Property) type, which are connected together to form complex systems. These systems may include systems of the multi-clock type that use multiple clock signals.
FIGS. 1a and 1b show in this context a generic system in which a transmitter component 1 transmits data over a communication channel 4 to a receiver component 6.
In the examples shown in FIGS. 1a and 1b, both of the components 1 and 6 are synchronous; namely, operation of the transmitter component 1 is synchronized with a clock signal CLK_TX, generated, for example, via a first oscillator 2, and operation of the receiver component 6 is synchronized with a clock signal CLK_RX, generated, for example, via a second oscillator 7.
Consequently, for transmitting the data generated by the component 1 to the component 6 interface systems 3 and 5 are necessary and configured for transmitting the data over the communication channel 4 taking into account the fact that the clock signals CLK_TX and CLK_RX may be phase-shifted with respect to one another or may even be different.
The person skilled in the art will appreciate that for the above purpose typically a dual-port First-In First-Out (FIFO) memory is used, where generally writing occurs with the clock signal CLK_TX of the transmitting circuit 1 and reading occurs with the clock signal CLK_RX of the receiving circuit 6.
For instance, in FIG. 1a the FIFO memory forms part of the reception interface 5 of the receiving circuit 6, whereas in FIG. 1b the FIFO memory is incorporated in the transmission interface 3 of the transmitting circuit 1.
In this context, FIG. 1c is a schematic illustration of a possible synchronous-communication scheme based upon a two-phase signaling protocol, i.e., communication is synchronized with a clock signal CLOCK, for example with the rising edge of the signal CLOCK.
In this case, it is possible to use a first control signal REQ for signaling that data are available on a bus DATA, i.e., that the data are valid, and a second control signal ACK for signaling that the receiver has been able to sample the data DATA.
In particular, in order to indicate the fact that no new data are available on the bus DATA, the signal REQ has a first logic value, such as for example the logic level ‘0’; namely, this condition corresponds to an initial step, referred to as RESET. Instead, when new data are available on the bus DATA (step FS1), the transmitter component changes at an instant t1 the logic value of the signal REQ; for example, it changes the logic level of the signal REQ from ‘0’ to ‘1’.
However, on account of propagation delays, this change is not immediately detectable, and the receiver can detect said change of the signal REQ only with the next rising edge of the signal CLOCK, i.e., at an instant t2.
Once the change of the signal REQ (step FA2) has been detected, the receiver component samples the data on the bus DATA and confirms that the data have been read; namely, the receiver component changes at the instant t2 the logic value of the signal ACK; for example, it changes the logic level of the signal ACK from ‘0’ to ‘1’.
Again, this change can only be detected at the next clock cycle, i.e., at an instant t3.
Consequently, when the transmitter component detects the change of the logic value of the signal ACK at the instant t3, transmission has gone through successfully and both of the components return to the initial condition, i.e., the condition RESET. However, in the case where a number of data must be transferred consecutively at the maximum speed, the signals REQ and ACK could even remain always high.
The above communication is synchronous, because, in order to generate and sample the control signals REQ and ACK, both of the components use one and the same clock signal, or else clock signals that have one and the same frequency.
Consequently, applying a similar synchronous protocol to FIGS. 1a and 1b:                 the data can be written in the FIFO memory with the clock signal CLK_TX, where a signal TX_REQ indicates a request for writing of data TX_DATA in the FIFO memory, and a signal TX_ACK indicates that the data TX_DATA have been written in the FIFO memory; and        the data can be read from the FIFO memory with the clock signal CLK_RX, where a signal RX_REQ indicates that data RX_DATA are available in the FIFO memory, and a signal RX_ACK indicates that the data have been read by the receiving circuit 6.        
However, in both cases it is necessary for the clock signals CLK_TX and CLK_RX to be brought up to the FIFO memory. Consequently, in the case where the circuits are far apart, one of the clock signals (signal CLK_TX in FIG. 1a and signal CLK_RX in FIG. 1b) is also subject to a long delay, which should be taken into account.
For this reason, as an alternative to a synchronous communication protocol, also an asynchronous communication protocol could be used.
For instance, FIG. 2a shows an example in which the interface 3 is configured for converting the synchronous communication generated by the transmitter circuit 1 into an asynchronous communication, and the interface 5 is configured for converting the asynchronous communication received from the interface system 3 once again into a synchronous communication.
Typically, asynchronous circuits are based upon a signaling protocol comprising four handshaking phases. In this case, the insensitivity to the delay is obtained via a particular encoding of the data; i.e., the validity of the data may be recognized also from the data themselves.
For instance, FIG. 2b shows a communication scheme based upon a four-phase signaling protocol, where the signal on a bus ADATA itself signals start of a new communication. In this case, a signal AACK for signaling that the receiver component has been able to sample the data is in any case expedient.
In particular, also in this case, both the transmitter component and the receiver component are in an initial condition referred to as RESET.
However, in order to signal start and end of a communication, the signal on the bus ADATA is directly used. For instance, typical four-phase protocols are the “Dual-Rail” or “1-of-N” protocols.
For example, in order to transmit the logic value ‘0’ (step FA1), it is possible to transmit in actual fact at an instant t4 the sequence of bits “01” on two different lines. In a substantially similar way, in order to transmit the logic value ‘1’, it is possible to transmit in actual fact the sequence of bits “10”.
The receiver component detects said signal on the bus ADATA and confirms that they have been read (step FA2); i.e., it changes the logic value of the signal AACK, for example, changing the logic level from ‘0’ to ‘1’.
Consequently, the transmitter component detects the change of the signal AACK at an instant t5, and the transmitter component signals the end of the communication at an instant t6 (step FA3). For instance, in order to signal the end of the communication, the transmitter component can transmit the sequence of bits “00”.
Finally, said sequence of bits is detected by the receiver component, and also this returns to the initial condition, i.e., the receiver component again changes the logic value of the signal AACK.
The transmitter component can detect this change at an instant t7 and terminate the communication (step FA4).
Hence, such a four-phase protocol can also be detected in an asynchronous way, i.e., at any moment.
For instance, the documents Nos. EP 2 466 477, EP 2 466 478 and EP 2 466 479, the contents of which are incorporated herein for reference, describe possible embodiments of the interfaces 3 and 5 that can be used for such an asynchronous communication.
The above asynchronous-communication systems hence solve the problem of the delays in propagation of the various clock signals. However, as mentioned previously, typically additional wires are required for implementing the asynchronous encoding, and, owing to the four-phase protocol, communication is typically slower.